In CMOS technology, typically the device isolation is accomplished with a locos process. For such a process, it requires a high field threshold voltage and an additional field implant is provided. The field implant is typically accomplished with n-type dopant for p-channel devices and a p-type dopant for n-channel devices. Usually this implant step is provided with a conventional energy and dose. The implant is also typically performed early in the process flow to ensure that the dopant is adequately placed therewithin.
Additionally, this dopant could also be utilized to minimize the transistors off-state leakage current which is present in the active device region. Since this implant is placed uniformly in the device area, it has been found however that for many cells or many semiconductor circuits, using this conventional process the junction breakdown characteristics are lowered and junction capacitance is significantly increased as a result. As devices become smaller and the impact of processing temperature cycles becomes more significant, these problems become more acute. Hence, it is desired that integrated circuits be provided that have improved device isolation as well as improved leakage current control without impacting junction breakdown characteristics and junction capacitance. Such circuits should be easy to manufacture and are compatible with existing processing requirements. The present invention addresses such a need.